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CSE 462 mips-verilog. 5 Memory From outside memory is 256 words of 8-bits each zSeparate writedata and memdata ports Internally 64 words of 32-bits each zUpper 6 bits of adr used to select which word zLower 2 bits of adr used to select which byte At initialization, loaded from a file named “memfile.dat” zWhose format is as a “.csv” like ...
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example, if a,b,c are in registers 8,9,10 ... MIPS RISC Load-Store architecture. Every operand must be in a register ; Except for some small integer constants that can The MIPS ISA Processor State 32 32-bit GPRs, R0 always contains a 0 32 single precision FPRs, may also be viewed as 16 double precision FPRs FP status register, used for FP compares & exceptions PC, the program counter some other special registers Data types 8-bit byte, 16-bit half word 32-bit word for integers
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9/17/13 3 Agenda • Decisions • Strings& • Administrivia& • String&Copy&Example& • Technology&Break& • Funcons • MIPS&register&allocaon&conven]on&
MIPS Technologies definition: (MIPS Technologies, Inc., Mountain View, CA, www.mips.com) Founded in 1984 as MIPS Computer Systems Inc., the company merged with SGI in 1992 and spun off as an independent entity once again in 2000.
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• Example: Only 32 registers in MIPS – Simplicity favors regularity – Good design demands compromise ... • Consider the load -word and store -word instructions,
Both “lw” and “sw” (store word) belong to I-format. MIPS has (fortunately) only three different instruction formats. The operation codes determine the format ...
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MIPS reference card add rd, rs, rt Add rd = rs + rt R 0 / 20 sub rd, rs, rt Subtract rd = rs - rt R 0 / 22 addi rt, rs, imm Add Imm. rt = rs + imm I 8 addu rd, rs, rt Add Unsigned rd = rs + rt R 0 / 21 subu rd, rs, rt Subtract Unsigned rd = rs - rt R 0 / 23 addiu rt, rs, imm Add Imm. Unsigned rt = rs + imm I 9 mult rs, rt Multiply {hi, lo} = rs ...
example, if a,b,c are in registers 8,9,10 ... MIPS RISC Load-Store architecture. Every operand must be in a register ; Except for some small integer constants that can
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Example of File I/O The sample MIPS program below will open a new file for writing, write text to it from a memory buffer, then close it. The file will be created in the directory in which MARS was run. # Sample MIPS program that writes to a new file.
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Immediate addressing Operand is help as constant (literal) in instruction word Example: ADDI $2, $3, 64. University of Pittsburgh. MIPS Instruction Set Architecture MIPS Addressing Modes (cont) MIPS addresses jump targets as register content or 26-bit pseudo-direct address Example: JR $31, J 128. MIPS addresses load/store locations
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2 Outline MIPS Architecture ISA –Instruction types –Machine codes Procedure call Stack Laboratory 2: Inlab MIPS: The Virtual Machine Laboratory 2: Inlab Date Section Name Addressing in MIPS During this exercise you will use the load word (lw) and store word (sw) instructions. Background The only way CPU can access the memory in MIPS is through load and store instructions. There is only one addressing mode (base+displacement).
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# hello.s # a sample MIPS program to demonstrate MIPS basics # Usage: $ spim -f hello.s .data # data segment begins here stuff: .asciiz "Hello World! " .text # code segment begins here main: la $a0, stuff li $v0, 4 # 4 is syscall to print a string syscall # execute the call li $a0, 10 # 10 is ascii value for linefeed li $v0, 11 # 11 is syscall to print char syscall li $v0, 10 # 10 is system call to exit syscall # execute the call
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